1. Field of the Invention
The present invention relates to the field of computer systems. More particularly, the present invention relates to accessing memories in computer systems.
2. Description of Related Art
A main memory is an important part of a memory subsystem of a computer system. The main memory typically includes an array of dynamic random access memories (DRAMs) that are configured to temporarily store application programs, other software codes for use by the computer system, and data. The performance of a memory is measured in terms of its ability to quickly respond to memory access requests from a processor.
A DRAM (hereinafter referred to as "memory") typically includes a plurality of rows and columns. Each row may include at least one page. An access to the memory (hereinafter "memory cycle") may typically be performed by a sequence of events where the Central Processing Unit (CPU), initially, generates an address (current address) to a local bus or host bus. A memory controller, coupled to the local bus, decodes the current address and accordingly determines which row and column of the main memory corresponds to the current address. Moreover, the memory controller drives the current address to the memory to select a page corresponding to the current address. Once the memory controller determines what row corresponds to the current address, a Row Address Strobe (RAS#) signal is generated and asserted to the respective row. The sign "#" following a name of a signal such as RAS, indicates that the respective signal is "active low", i.e., the respective signal causes a certain effect when that signal is at "0" logic. Subsequently, while the RAS# signal is asserted to the addressed row and a page is selected in that row, the memory controller asserts a Column Address Strobe (CAS#) signal to an addressed column. After CAS# is asserted, the DRAM typically either provides data, i.e., a read operation, or latches data, i.e., a write operation. Typically, at the beginning of a memory access cycle, both RAS# and CAS# are deasserted and are kept deasserted for at least an amount of time equal to a respective precharge times for these signals. The concept of RAS# and CAS# precharge is well-known in the art.
To increase the speed of a memory cycle, some users configure the memory controller to utilize page hit cycles. A page hit cycle (hereinafter referred to as "page hit") is defined as: a memory cycle where a current row address is the same as the row address generated by the CPU during a most recent memory cycle; and the RAS# signal for that respective row is asserted. A page hit requires fewer clock cycles to be completed for a memory cycle because the RAS# signal is already asserted at the beginning of the cycle thereby avoiding the time incurred by the RAS# precharge time.
A "page miss" occurs when the current address differs from the previous address but the row corresponding to that address is the same as the most recently addressed row. A "row miss" cycle occurs when a page currently addressed is found in a row different than the most recently addressed row. A row miss cycle requires that a new RAS# signal corresponding to a currently addressed row is asserted to that row. Such access is slower than a page hit where RAS# remains asserted, as the system must wait for the appropriate different RAS# signal to settle in its asserted state before the CAS# signal is asserted. However, a row miss cycle typically requires less clock cycles than a page miss cycle since the system requires that the RAS# signal be deasserted and then asserted to the same row while the new address is presented to the memory. This causes the system to wait for the RAS# signal to settle in its deasserted state and then to settle in its asserted state, before the CAS# signal is asserted.
It has been found that the number of memory cycles needed to access a memory may be different for different system architectures. Also, the number of memory cycles needed may differ depending on whether a page is left open or a page is closed. Furthermore, depending on the system's architecture, occurrence of certain events in the system, such as a cycle abort, may affect the number of needed memory cycles. For example, it has been determined that when a page miss or row miss cycle occurs and that cycle is thereafter aborted, systems endowed with a second level cache may need a different number of memory cycles, depending on the state of the pages addressed, i.e. page open or page closed.
It is desirable to provide a paging process and a computer system that implements a paging process that efficiently controls the opening and closing of pages and takes into account the system architecture and the occurrence of certain events in the computer system such as the host bus being idle, a cycle being aborted, etc.